Position Details
Job Description
Participate in feasibility studies and sub-block/chip-level architecture definitionDesign and integration of digital sub-blocks and chip-level implementationVerification planning and Block/Top level direct testingSupport DFT strategy and implementationWork closely with back-end designers to correctly implement digital designs to layoutBlock/Top level LINT/CDC/RDC/STA/LEC setup and checksLab evaluation and debugging of digital blocks and full chip functionSupport production testing, HW/SW development and device characterizationTape out database and documentation preparationIC design reviews, consultations and risk assessmentsParticipation in project meetings, training courses and conferencesDemonstrates an ability to learn new tool features and procedures
Qualifications
Master’s or Ph.D. in Electrical Engineering or related disciplines...