Staff Design Verification Engineer

Job Description

+ Do design verification
+ Create Vplan (checking item)
+ Write test program
+ Execute test program
+ Confirm verification result

Job requirements:

+ Good experience in verification skill set.
+ Experience in Vplan (verification plan) making from TS (target specification)
+ Experience in task pattern (C language, ASM ) from Vplan
+ Experience in conduct verification result including coverage judgement
+ Familiar with simulator/debuger VCS/Verdi/XLM/Indago
+ Knowledge about SystemVerilog and UVM
+ Knowledge about AMBA protocol: AHB, APB, AXI is a must.
+ Basic knowledge of Formal verification, SVA, TCL.
+ Have knowledge about assembly, C/C++, Verilog languages.
+ Knowledge about Functional Safety, ISO26262 is a plus
+ Provide transparent information, be agile in daily operations.
+ Communicate fluently with teams and customers with a global mindset.
+ Be...