This incredible design team is seeking a dynamic and highly motivated senior DFT engineer who will participate to the design of a state-of-the-art CMOS Transceiver ASIC for the Communications market.

You will drive and execute the definition and implementation of DFT in the chip in closed relationship with the physical implementation as well industrialization teams.

Work description

Responsible for the DFT architecture and drive and execute the DFT implementation of a complex SOC in advanced CMOS process (sub 20nm technologies)
Responsible for the development of a DFT flow (HW DFT insertion, test vectors generation, validation)
Responsible for the analysis of digital DFT metrics of proposed DFT solutions in view of the DFT requirements (test time, yield and default rate).
Advise digital design engineers on designing testable functional modules
Work closely with the RTL design team, physical implementation team to ensure a seamless ...