Job function:

Our client's Layout Team is seeking a dynamic and highly motivated Layout Engineer to work on physical implementation and verification of analog and mixed-signal ASIC functions to deliver state-of-the-art Integrated Circuit (IC) in deep submicron CMOS technology.

Work description:

* In close collaboration with analog, mixed-signal and digital designers, define the ASIC floorplan and its sub-blocks, input / output pin placement and top-level assembly
* Full-custom physical implementation of high speed and high-performance analog, mixed-signal blocks including integration of digital macros.
* Optimize the layout to meet circuit area and performance requirements
* Optimize the layout with respect to voltage drop, matching, speed and coupling.
* Perform sign-off physical verification of sub-blocks and/or top chip meeting all manufacturing requirements (DRC, LVS, ERC, EM)
* Generate post-layout netlist with parasite ext...