Join Alphawave Semi as an RTL Design Engineer focusing on complex IP implementation and timing strategies. Enhance high-speed data communication for technologies like AI and 5G.

As an RTL and Timing Design Engineer, you will be responsible for the entire front-to-back implementation workflow for high-performance computing systems. Leveraging your SystemVerilog expertise, you will manage timing constraints and optimize power analysis. Your role will involve close collaboration with cross-functional teams to ensure design quality and facilitate cutting-edge innovations in data communications.

Key Responsibilities

• Own the implementation of complex IP from RTL to P&R;
• Conduct synthesis and interpret QoR timing reports
• Manage timing constraints and triage violations
• Define clock architecture and CTS targets
• Integrate AI tools for log analysis and recommendations

Requirements

• Bachelor's/Master's...