Cpl are partnering with a market leading semiconductor organisation to appoint an experienced Principal Verification Engineer. This is a senior technical role within a high‑performing IP development team, focused on the verification of advanced DDR memory controllers used in next‑generation systems across datacenter, AI, automotive, and edge computing markets.

The Role

The successful candidate will take ownership of verification architecture and execution for complex controller IP, contributing at both a hands‑on and strategic level.

Key responsibilities include: