At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

The candidate will have the opportunity to work on many varieties of challenging designs, i.e. low power and high speed design. As well as participating in or leading next generation PHY IP physical design, methodology and flow development, the candidate will work closely with our RTL design team & Analog Team to ensure successful tapeouts.

Main Job Tasks And Responsibilities

• Participating in or leading next-generation physical design, methodology, and flow development in advanced technology nodes.
• Perform physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure.

Position Requirements