Position Details
Lead Mixed Signal Verification Engineer
Interact with analog design team and develop behavioral models of analog design blocks in System Verilog realIntegrate the SV real behavioral models in top level verification environment; provide debug support for models as and when neededDo periodic DMS netlist generationContribute to the DMS testplan --- add description of testcases for verifying A-D connectivityDevelop checks in the form of System Verilog assertionsDevelop DMS testcases and debug them in case of test failuresDevelop AMS simulation environmentDevelop AMS testplan – capture what all testcases make sense for AMS simulationsRun AMS testcases and review waveforms with analog design team