FPGA Design Engineer
JOB RESPONSIBILITIES

RTL block design (SystemVerilog / Verilog / VHDL)

FPGA system assembly with in-house blocks, vendor macros and reference-designs.

Testbench creation and design verification

FPGA implementation in Xilinx Vivado tool-set, with complete timing constraints.

Setup and debug with Xilinx ILA

Potential collaboration with hardware, software, analog/digital IC design engineers.

REQUIREMENTS

Degree in Electrical/Electronic Engineering or similar technical field.

Minimum of 5 years of experience in IC or FPGA design, with 5-10 years in industry.

Able to understand both Verilog/SystemVerilog and VHDL

PREFERENCES

Experience with Xilinx Unltrascale+ devices

Experience working with DDR RAM controllers and efficient memory access

Prior experience with high-speed interfaces (DPHY, LVDS, GbE) on FPGA a significant advantage.