Working for a leader in power in power electronics, this is a great opportunity to join a growing team, as UVM verification engineer.

Job duties:

Developing test plans, tests and verification infrastructure using SV/UVM methodology

Building reusable bus functional models, monitors, checkers and scoreboards

Performing coverage driven verification closure

Performing block level, multi-block level and system-level verification

Performing Gate level simulations

Performing Mixed Signal simulations

Implementing Regression tests

Performing Formal Verification

Working closely with IC designers and post-silicon engineers

Qualifications and Background
 
Requirements:

Knowledge/experience with HDL (SystemVerilog / Verilog / VHDL), particularly for testbenches creation

Knowledge/experience in scripting languages, such as Tcl and Python<...