Commitment: Full-time preferred; high availability required (40 hours)

Duration: Target engagement of ~3+ months

Location: Remote, USA and Canada only

RTL Design Engineer Qualifications

3-10 years of experience in digital RTL design

Strong proficiency in Verilog / SystemVerilog

Solid understanding of digital design fundamentals: FSMs, datapaths, pipelines, FIFOs, arbiters, clock/reset domains, bus protocols

Experience with ASIC design flows: lint, synthesis, timing analysis, CDC, DFT-aware design

Familiarity with common EDA tools for simulation, waveform debug, lint, CDC, synthesis, timing analysis

Familiarity with leveraging LLM-based tools to accelerate chip design, RTL development, debug, documentation, or verification workflows

Ability to write clear design documentation and communicate technical tradeoffs

Experience debugging RTL issues using simulation logs and waveform viewers
...